14.00 - 14:10

Introduction to the Workshop

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14:10 - 14:30

Pathfinding PDK, a Window to the Future Technologies

Julien Ryckaert (imec, BE)

With the scaling of semiconductor technologies following eclectic trajectories, the need for pathfinding PDKs is becoming a necessity. Indeed, moving away from pure miniaturization, advanced technology nodes end up creating larger and larger disruptions in the design of modern SoCs. Device architecture changes, 3D and 2.5D integration, backside technology, among others, all contribute to computing system scaling nowadays. However, extracting the best PPA they may offer sometimes requires a profound revision of longestablished design practices. Opening these disruptions and their consequences to a larger group of experts can only benefit the ecosystem. The N2 P-PDK with BSPDN is a step aimed at rallying a community to this fascinating new era of computing scaling.

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14:30 - 14:50

Innovation to Enable Physical Design for Advanced Process Nodes

Rod Metcalfe (Cadence Design Systems, UK)

Imec world class advanced process node research projects have resulted in many innovations, enabling scaling down to angstroms. As part of this research, it is critical to ensure EDA tools are ready to implement these new, and often challenging, concepts. Cadence and Imec have been collaborating on 3D-IC, test, nano-sheet, CFET and other topics for over 10 years, developing EDA implementation technology to support the latest advanced process requirements. The most recent example is the Imec N2 PDK pathfinding project, which was developed using the complete Cadence digital flow. During this session we will show how Imec and Cadence collaboration has resulted in N2 PDK place & route, and backside implementation flows, which are now widely available for further academic research.

 

14:50 - 15.10

Partnering for System Technology Co-Optimization: Collaboration on EDA and Advanced Technologies as we March towards Angstroms

Jared Anderson (Synopsys, FR)

Design complexity is ramping up from the silicon level to the system level while at the same time underlying silicon technology is rapidly evolving. Multi-die and 3DIC solutions are being introduced to partition and implement designs in the most efficient manner.
Partnering at the system level allowed Synopsys to enable IMEC engineers to define fully optimized logical and physical architectures for their systems. Finally, the key to being able to implement all of this is the rapid development and deployment of advanced node PDKs that can handle new features such as nanosheet devices and backside power delivery. Use of Synopsys's RM flow gave a scalable and efficient way for IMEC to migrate their PDK validation flows to newer technology nodes.

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15:10 - 15:30 

​Exploring Next-Generation Many-Core RISC-V Architectures on Future CMOS Technologies: Mempool3D and beyond

Luca Benini (University of Bologna, IT)

 

15:30 - 16:00

Coffee break 

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16:00 - 16:20

Challenges in Upcoming CMOS Heterogeneous design Triggered by Technology Paradigm Shift

Marisa López-Vallejo (Universidad Politécnica de Madrid, ES)

​One of the promising solutions in CMOS design that enables versatile functionality suitable to a large variety of applications are chiplets: modular, customizable chips connected through high-speed interconnects. However, as CMOS technology is entering uncharted territory by shifting from FinFET devices to Nanosheet transistors, the chiplet design is facing numerous challenges. Decisive technology changes such as back-side power delivery network and interconnects and dense pitch copper bonding, to name just a few, have a direct impact on the chiplet power, performance and area. Having the latest technology models available during the design time will be a game changer to enable the most innovative solutions in chiplet design. We plan to discuss these challenges and the importance of having access to advanced technology during CMOS heterogeneous design. 

We plan to discuss these challenges and the importance of having access to advanced technology during CMOS heterogeneous design.

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16:20 - 16:40

Abstracting Device-Level Properties for System-Level Analysis and Design Space Exploration

Zain Navabi (Worcester Polytechnic Institute, US & University of Tehran, IR)

​The complexity of modern digital systems and the need for multi-aspect considerations in SoC and Embedded Systems design have led to the development of SoC frameworks and Virtual Platforms. These platforms integrate various design aspects, such as hardware, software, analog, and digital, for system-level analysis and design space exploration (DSE). The silicon technology node serves as a common denominator for all design aspects, requiring characterization and back-annotation for system-level use. The work presented focuses on the utilization of processor cores in an SoC with power considerations. Decisions about software algorithms, hardware accelerators, custom instructions, and different architectures significantly affect the SoC's power and area. To meet this requirement, the power properties of a specific technology node need to be characterized and back-annotated into a power model. This model runs in parallel with the processor instruction set simulator (ISS) and produces a detailed power trace of the instructions
being executed. Gate models have been developed that capture technology node information in individual System classes for each library cell. These models bridge the gap between lower-level physical implementations and upper-level system representation. The back-annotation process involves training a Neural Network model that runs in parallel with the processor ISS.
The system-level power modeling has been validated using open-source SoC frameworks with RISC-V processors, standard bussing systems, accelerators, and arithmetic coprocessors. The DSE environment has been evaluated for various uses of accelerators and software algorithms.

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16:40 - 17:20

Panel discussion

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17:20 - 17:30

Conclusion

​Julien Ryckaert

Julien Ryckaert received the M.Sc. degree in electrical engineering from the University of Brussels (ULB), Belgium, in 2000 and the PhD degree from the Vrije Universiteit Brussel (VUB) in 2007. He joined imec as a mixed-signal designer in 2000 specializing in RF transceivers, ultra-low power circuit techniques and analog-to-digital converters. In 2010, he joined the process technology division in charge of design enablement for 3DIC technology. Since 2013, he is in charge of imec’s design- technology co-optimization (DTCO) platform for advanced CMOS technology nodes. In 2018, he became program director focusing on scaling beyond the 3nm technology node as well as the 3D scaling extensions of CMOS. Today, he is vice president logic in charge of compute scaling.
 

Rod Metcalfe

Rod Metcalfe is a Senior Group Director in the Digital and Signoff product management team at Cadence, responsible for digital implementation flows and artificial intelligence technology development. He has been involved with EDA for over 20 years, gaining experience in all parts of the digital design flow from synthesis to sign-off. Before joining EDA, Rod was a chip designer in the aerospace industry.

Jared Anderson
Jared is a senior Architect at Synopsys. He is a member of the Advanced Node Methodology Pathfinding team which is responsible for rapid PPA closure on high-performance designs using Fusion Compiler. Ared holds a Bachelor of Engineering in Computer Systems with First Class Honors from the University of Queensland, Australia. He works very closely with Synopsys R&D and Foundry Partners on bleeding-edge technologies, helping to enhance EDA engines for improved PPA and isolating potential issues for customer-specific designs. This requires hands-on analysis of engine issues and providing quick solutions (usually TCL/Python prototypes) to show that these engines can be extended to meet the foundry or customer’s needs. Jared often engages with early new node customers while supporting the deployment of the latest technologies. He can also act as the Synopsys spokesperson to our Foundry partners.
 

Luca Benini

Luca Benini holds the chair of digital Circuits and systems at ETHZ and is Full Professor at the Università di Bologna. His research interests are in energy-efficient parallel computing systems and machine learning hardware. He is a Fellow of the IEEE, of the ACM and a member of the Academia Europaea. He is the recipient various awards, including the 2023 IEEE CS E.J. McCluskey Award.

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Marisa López-Vallejo

Marisa López-Vallejo received the M.S. and Ph.D. degrees from the Universidad Politécnica de Madrid, Madrid, Spain. She is Full Professor at the Department of Electronic Engineering, Universidad Politécnica de Madrid. She has worked as a technical staff member at Lucent Technologies, Bell Laboratories, Murray Hill, NJ, USA. During the academic year 2015-2016 she was a visiting professor at the Microsystems Technology Lab, MIT, USA. Her research interests include low power, process voltage, temperature-aware design, computer-aided diagnostic methods and tools, and application-specific high performance programmable architectures. Over the past decade, her research has focused on the reliability of CMOS circuits and memristive memories, and on new architectures to support reliable computing at the deep nanometer scale. She has coordinated a number of national and international (EU) projects in these areas. She has supervised 12 PhD theses and has published more than 100 papers in journals and conferences in the field.
 

Zainalabedin Navabi

Zainalabedin Navabi is an adjunct professor of electrical and computer engineering at Worcester Polytechnic Institute, and professor of ECE at the University of Tehran. He is the author of several textbooks and computer-based trainings on VHDL, Verilog and related tools and environments. Dr. Navabi’s involvement with hardware description languages (HDL) begins in 1976, when he started formal definition of a register transfer level HDL and development of a simulator for it. In 1981 he completed the development of a synthesis tool for that same HDL. The synthesis tool generated MOS layout from an RTL description. Since 1981, Dr. Navabi has been involved in the design, definition, and implementation of Hardware Description Languages and design methodologies. His work on HDLs has continued to languages used today for system-level design and modeling and language-based design space exploration (DSE) methodologies. New domain-specific languages and methodologies for AI and ML are part of his on-going work.