​14:00 - 14:15

Process Integration of 3D Vertical Junctionless Transistors

Guilhem Larrieu (LAAS-CNRS, Toulouse, FR) 

​With the continuous advancement toward nanometer technology nodes, device architectures have become increasingly complex, integrating dimension shrinking and new integration schemes to enhance device density. The Gate-All-Around (GAA) architecture is poised to supersede the FinFET architecture for nodes below 3 nm, aiming to improve drive current capability, enhance channel control, reduce leakage currents, and decrease dynamic power consumption. Vertical Transport GAA devices offer significant potential for denser devices by minimizing contact pitch and utilizing a 3D configuration to mitigate routing congestion. This talk discusses the current state-of-the-art demonstrations and limitations of such architectures, particularly in gate length scaling and 3D contact assessment. Additionally, the concept of 3D integration of multiple device stacking will be introduced.​​

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14:15 - 14:30

Reliability Analysis of 3D Vertical Nanowire Transistors 

Yifan Wang (University of Bordeaux, FR)

​In sub-20 nm transistors, miniaturization imposes more critical constraints on device performances leading to reliability issues. The understanding of the failure mechanisms of emerging transistor technologies requires more research data and evidence. In this research, we conducted the first reliability investigation on the emerging technology of junctionless vertical nanowire transistors (VNWFETs). We first performed temperature storage tests and then conventional negative bias-temperature instability (NBTI) accelerated aging tests on the VNWFETs from LAAS CNRS, which exhibited gradual degradation of the device. The two tests are performed in order to dissociate the impact of pure temperature and bias-induced degradations. In both cases, a variation of device threshold voltage with the stress time is observed which helped us analyze the degradation and recovery mechanisms in the vertical nanowire technologies.

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14:30 - 14:45

Integration of Ferroelectrics into 3D Nanowire Devices 

Konstantinos Moustakas (LAAS-CNRS, FR)

​Since the discovery of ferroelectricity in Hafnium oxide (HfO2) in 2011, significant research efforts have focused on its exploration. Various dopants have been proposed to enhance its ferroelectric properties, with hafnium zirconium oxide (HZO) emerging as the most prominent. While HfO2 is compatible with CMOS technology as a high-k dielectric, integrating it as a ferroelectric gate dielectric presents challenges for applications in ferroelectric devices. These challenges include identifying proper crystalline phases, optimizing activation anneal temperatures and layer stability, devising strategies for electrical characterization involving cycling and retention, and developing fabrication approaches. Additionally, as the FET architecture roadmap shifts towards 3D concepts, new challenges arise in integrating ferroelectric materials into miniaturized vertical devices, necessitating innovative approaches. This workshop will showcase the latest developments in various HZO integration concepts as ferroelectric materials, assessing their electrical performance at the layer and device levels. Finally, it will address challenges related to integrating ferroelectric layers in vertical configurations with respect to a junctionless nanowire technology.

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14:45 - 15:00

Material and Device Development for Ferroelectric Nanowire Transistors with TCAD 

Mischa Thesberg (Global TCAD Solutions GmbH, AT) 

Over the past decade there has been a great renewal in interest towards harnessing the intrinsic non-volatile nature of ferroelectric films for use in semiconductor devices. This renewed interest has been spurred by the discovery of new ferroelectric materials, such as hafnium zirconium oxide (HZO), suitable for usage in nano-sized modern devices. TCAD simulation has played an important role in the development and study of these new materials and new proposed devices. However, TCAD modeling of ferroelectric materials is a challenging, multi-aspect endeavour that requires careful consideration of the underlying models and physics. Amongst these challenges are: making sense of the great variety of competing and often physically inconsistent models proposed in the literature, the almost always polycrystalline natures of such films leading to important 3D effects and variability, and the often dominant role played by the interaction of ferroelectric and charge trapping that often requires a great understanding of the subtle relationship between the models used in both aspects. In this workshop a pedagogical introduction to the subject of ferroelectric modeling in TCAD will be given. Special attention will be given to the modeling of modern nano-scaled films and on issues of 3D effects and the interplay with charge-trapping physics.

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15:00 - 15:15

Test Structure Design Optimization for Emerging Technologies 

Marina Deng (University of Bordeaux, FR)

New nanowire transistor technologies have emerged to address in-memory computing applications or even increase systems’ functionality compared to conventional planar technologies. But these emerging nanowire transistors cannot be characterised without optimising the associated test structures. For instance, the compact modelling of these transistors is based on precise measurements, particularly at microwave frequencies, in order to extract specific model parameters. The impact of the parasitic interconnect needs to be minimized to provide reliable high-frequency measurements. This can be achieved by a thorough examination of the technology process leading to optimized test structure design.​​

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15:15 - 15:30

Characterization, Parameter Extraction, and Compact Modeling of Emerging Technologies 

Chhandak Mukherjee (University of Bordeaux, FR)

This lecture focuses on experimental techniques for characterizing and parameter extraction for compact modeling of emerging nanoscale technologies. With the advent of new device architectures and topologies, applicability of conventional experimental methods has become limited and novel methods are required to be derived and developed. Consequently, reinventing the design value chain would also require accurate models for circuit and system level design. One of the biggest challenges associated with characterization is to ensure high accuracy of electrical measurements which is not straightforward due to several factors such as maturity, variability and stability of the technology. This also puts in question the preliminary models developed for the technology. Design technology co-optimization (DTCO) at early stages is therefore highly reliant on developing accurate characterization methods which in turn play an important role in the improvement of technology maturity.

This lecture illustrates, with the example of a junctionless vertical nanowire transistor technology, different characterization methods (DC, RF, electrothermal, noise, etc.) developed for these non-planar and non-conventional technologies. These characterization methods enable accurate extraction of important device parameters for reliable model development, thereby facilitating novel circuit design activities based on these 3D technologies.

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15:30 - 16.00

Coffee break

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16:00 - 16:20

Design-Technology-Co-Optimization Flow Using the GTS Framework 

Zlatan Stanojevic (Global TCAD Solutions GmbH, AT) 

​With the introduction of new device architectures and scaling boosters, Design-Technology Co-Optimization (DTCO) becomes increasingly important in technology path-finding, aligning design and technology parameters to optimize cell or even system performance. TCAD is key to DTCO as it allows for predictive simulations, exploring device structures, materials, process variations, and device degradation. To overcome the practical limitations imposed by the computational and memory demand of TCAD simulations, a combination with SPICE can be leveraged where the SPICE circuits and models are extracted accurately from TCAD. As a physics based approach, TCAD simulations allow to naturally include variation and degradation mechanism, hence TCAD-to-SPICE flows can be augmented with such and allow for reliability and variability-aware design flows, enabling path-finding and benchmarking of design and technology options with short turnaround-times.
In this talk, the basics of DTCO simulation will be introduced and a handful of key specific examples explored to provide a comprehensive introduction to this important and growing field.
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16:20 - 16:40

Reconfigurable and Ferroelectric Transistors – From SOI Devices to 3D-Gates

Jens Trommer (Namlab gGmbH, DE)

Reconfigurable Field Effect Transistors (RFETs) and Ferroelectric Field Effect Transistors (FeFETs) are two emerging device technologies, which have recently proposed to be co-integrable directly into industrial 22 nm FDSOI technology. By serving as an add-on techology both emerging devices can be used to introduce a higher functionality to the system, without the need for scaling the individual device size. In this talk, similarities and difference between ferroelectric and reconfigurable logic gate designs are illustrated and its related constraints for system level design in a 3D platform are reviewed.

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16:40 - 17:00 

Circuit Stepping Stones: Library Generation for 3D Logic and NV-Logic 

Ian O’Connor (Institut des nano-technologies de Lyon, FR)

Vertical Nanowire Field Effect Transistors (VN-WFETs) are an emerging technology with significant potential to reduce footprint and consequently interconnect capacitance, thereby achieving improved energy-efficiency and being naturally compatible with advanced 3D integration approaches. However, while initial estimations have focused on projections and estimations, no work has so far used a detailed compact model to attempt accurate transistor-level simulations for standard cell library characterization thus enabling logic synthesis. In this work, we propose a design flow to make the link from an existing (laboratory-scale) VNWFET technology and the associated compact model, to standard static logic cell design and characterization, and ultimately logic synthesis. We will round off the discussion with some open problems in the logic synthesis landscape to incorporate non-volatile logic and reconfigurable universal logic gates.

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17:00 - 17:15

N2C2 - A Neural Network Compute Cube Accelerator for Transformer Applications 

Alberto Bosio (Institut des nano-technologies de Lyon, FR)

​In the realm of edge computing, the demand for zettascale data processing has elevated the need for enhanced performance, all while adhering to strict constraints such as energy efficiency, real-time execution, communication bandwidth, security, and privacy. Meeting these requirements necessitates more efficient hardware processors capable of executing computational tasks with low latency and minimal energy consumption. In this talk, we will describe a versatile and scalable Processing Element (PE) called the Neural Network Compute Cube (N2C2). Its principal function is to carry out element-wise non-volatile matrix multiplication, accumulation and activation through a non-linear function. It features multiple means of configuration, 1.) number of inputs to each cell: configure the vertical routing of data between layers in both directions. 2.) synaptic coefficients: program coefficients in memory elements and connect them to the multipliers, 3.) various activation functions can be efficiently programmed in memory elements in a coarse-grain logic-in-memory approach. We implement logic and physical synthesis on a "toy" scaled-down 4-bit N2C2 circuit using a library of VNWFET-based logic cells with the extracted timing, power and layout characteristics. This makes use of specific libraries as well as place and route methods and tools for the physical design of N2C2. We then explore a regular 3D matrix of configurable logic functions to build a Systolic Array accelerator for matrix-to-matrix multiplication and assess VNWFET scalability compared to traditional CMOS technology for data sizes ranging from 4 to 32 bits. Overall, this work a) establishes a full toolchain from device to complex logic block and b) enables the gathering of first insights into the actual design, performance and cost of the N2C2 block based on vertical technology.

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17:15 - 17:30

The FVLLMONTI Vision – A Lightweight in-Ear Device for Direct Speech-to-Speech Translation Enabled by Neural Network Transformers in 3D 

Cristell Maneux (University of Bordeaux, FR) 

This talk is about three-dimensional (3D) stacked hardware layers for machine translation. To provide an innovative solution for applications such as machine translation without relying on sending information to the cloud, it is essential to fabricate, model and simulate transistors that are really, naturally, 3D. The chosen disruptive technological approaches are based on ferroelectric vertical nanowire field-effect transistors (VNWFETs) to produce 3D stacked hardware layers of neural networks. These approaches give access to a denser processing unit allowing more processing power required for efficient neural networks. Creating 3D transistors, using nanowires, give access to naturally 3D crossbars, perfectly fitting to the neural network architecture. Another important feature is the memory points as an embedded memory in-logic element, therefore using ferroelectric gate transistors is mandatory. While being a general-purpose technology, it is used to demonstrate its power (in terms of accuracy, consumption, compactness and reliability) in the translation tasks using Transformers neural networks.

FVLLMONTI (Ferroelectric Vertical Low energy Low latency low volume Modules fOr Neural network Transformers In 3D) has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement no.101016776